1) Field of the Invention
The present invention relates to an information processing terminal and a transfer processing apparatus for transferring information to a different information processing terminal or a like apparatus by a DMA (Direct Memory Access) transfer method.
2) Description of the Related Art
First, a common platform which uses an information processing terminal which transfers (transmits) information (data) to a different processing terminal or a like apparatus by a DMA transfer method is described with reference to FIG. 15. FIG. 15 is a schematic view showing an example of a construction of a common platform. As shown in FIG. 15, an information processing terminal 100 which performs data transfer is connected to a different information processing terminal 110 which receives data transferred thereto through a connection apparatus for performing data transfer such as a LAN (Local Area Network)/WAN (Wide Area Network) 111, a public circuit 112 or a radio communication network 113.
Next, a configuration of a conventional information processing terminal (refer to, for example, patent documents 1 to 4 hereinafter listed) having a DMA transfer function is described with reference to FIG. 16. FIG. 16 is a block diagram showing a functional construction of the conventional information processing terminal 100. As shown in FIG. 16, the conventional information terminal 100 which performs data transfer by the DMA transfer method includes a central processing section 101, a transfer processing section 102 and a shared bus 103. The central processing section 101 produces main data to be transferred to the outside, information (that is, a header part) regarding the main data and a different information processing terminal 110 which is a transfer destination of the main data, and a descriptor for requesting transfer to the transfer processing section 102 described below. The transfer processing section 102 transfers data to the different information processing apparatus 110 based on the information (data) produced by the central processing section 101. The shared bus 103 is used to exchange data between a plurality of devices.
The transfer processing section 102 includes a shared bus controlling section 104 for controlling data transfer of the shared bus 103, an external port controlling section 105 for controlling transfer of main data received from the central processing section 101 through the shared bus 103 to a different information processing terminal 110, and a data transfer controlling section 106 for controlling the shared bus controlling section 104 and the external port controlling section 105 to control data transfer from the central processing section 101 to the different information processing terminal 110.
Here, operation of data transfer by the information processing terminal 100 is described with reference to FIGS. 17 to 20. FIG. 17 is a view illustrating an example of data produced by the central processing section 101 of the conventional information processing terminal 100 shown in FIG. 16; FIG. 18 is a view showing a format of a descriptor to be produced by the central processing section 101 shown in FIG. 17; FIG. 19 is a view showing an example of descriptors chained by a descriptor chaining method; and FIG. 20 is a time chart illustrating a flow of data on the shared bus 103 upon data transfer by the information processing terminal 100 shown in FIG. 17. It is to be noted that, in FIG. 17, like elements to those of FIG. 16 are denoted by like reference characters.
As shown in FIG. 17, where the same main data D is to be transferred from the information processing terminal 100 to a plurality of different information processing terminals 110 (here, a, b, . . . , n), the central processing section 101 first produces main data D and then produces header parts Ha, Hb, . . . and Hn for the information processing terminals a, b, and n which are transmission destinations, respectively. Then, the central processing section 101 individually combines the header parts Ha, Hb, . . . and Hn with the main data D to produce transfer data Ta, Tb, . . . and Tn and stores them. Here, each of the header parts Ha, Hb, . . . and Hn includes information (an address of a transfer destination of data and information of the transfer destination) of the information processing terminal a, b, . . . or n which is a transfer destination, information regarding a transfer source of the main data D, that is, the information processing terminal 100, and information regarding identity of the main data D such as a data length and a checksum of the transfer data Ta, Tb, . . . or Tn.
Then, the central processing section 101 produces descriptors (data transfer descriptors) Da, Db, . . . and Dn individually for the transfer data Ta, Tb, . . . and Tn, and issues a notification of the descriptors Da, Db, . . . and Dn to the transfer processing section 102 through the shared bus 103. Consequently, for each of the information processing terminals a, b, . . . and n, a request for transfer of the transfer data Ta, Tb, . . . or Tn is issued to the transfer processing section 102 (refer to an arrow mark (1) in FIG. 17).
A format of the conventional descriptors Da, Db, . . . and Dn produced by the central processing section 101 is illustrated in FIG. 18. The conventional descriptor shown in FIG. 18 is produced using a descriptor chaining method capable of forming descriptors relating to each other as a string of descriptors. Further, the conventional descriptor is formed so as to include an address of a transfer source of data (an address on the central processing section 101, information of a storage source) D10 which indicates a storage source of the transfer data, a transfer byte length D20 which indicates a data length of the transfer data, a C (Chain) flag D30 which indicates whether or not the descriptor is to be chained, a next descriptor address D40 which indicates a place (an address on the central processing section 101) in which a next descriptor is stored where the descriptor is to be chained. It is to be noted that a reference character RSV (Reserved) in FIG. 18 indicates a free area of the descriptor.
Accordingly, in order to issue a notification of a plurality of descriptors from the central processing section 101 to the transfer processing section 102, as shown in FIG. 19, the C flag D30 of any of the descriptors is set to “1” and a next descriptor address (here, 0xZZZZ) is written into the next descriptor address D40. Consequently, the plural descriptors are chained with each other and are successively read out from the central processing section 101 to the transfer processing section 102. Then, the C flag D30 of the last descriptor is set to “0”, and consequently, the chain of descriptors is ended with this descriptor.
Incidentally, if the descriptors Da, Db, . . . and Dn are transmitted from the central processing section 101 to the transfer processing section 102 to request the transfer processing section 102 for data transfer (refer to an arrow mark (1) in FIG. 17), then the transfer processing section 102 successively reads out the transfer data Ta, Tb, . . . and Tn from the central processing section 101 based on the descriptors Da, Db, . . . and Dn and transfers the read out transfer data to the different information processing terminal 110 (refer to an arrow mark (2) in FIG. 17).
In particular, the central processing section 101 produces a number of header parts and main data equal to the number of different information processing terminals 110 which are transfer destinations and produces a number of descriptors equal to number of different information processing terminal 110 which are transfer destinations and issues a request for data transfer to the transfer processing section 102. Then, if the request for data transfer is detected, then the transfer processing section 102 starts transfer of the data to perform transfer of the object data of the request.
Operation of data transfer by the information processing terminal 100 and a flow of data passing the shared bus 103 in the process just described are described. It is assumed here that, in the information processing terminal 100, the descriptor and the header part are transmitted from the central processing section 101 to the transfer processing section 102 through the shared bus 103 in 1 t (t indicates a unit of time, a control clock unit), and the main data D is transmitted from the central processing section 101 to the transfer processing section 102 through the shared bus 103 in 2 t.
As shown in FIG. 20, when the information processing terminal 100 transfers the main data D to the information processing terminals a, b, and n, the descriptor Da for the information processing terminal a first passes the shared bus 103 and is transmitted from the central processing section 101 to the transfer processing section 102 (refer to reference character t1 in FIG. 20).
Then, in accordance with the descriptor Da, the header part Ha for the information processing terminal a and the main data D paired with each other, that is, the transfer data Ta, passes the shared bus 103 and is transmitted from the central processing section 101 to the transfer processing section 102 (refer to reference characters t2 to t4 in FIG. 20). At this time, the data transfer controlling section 106 of the transfer processing section 102 controls the shared bus controlling section 104 based on the descriptor Da for the information processing terminal a to read out the transfer data Ta from the central processing section 101 as described above, and then controls the external port controlling section 105 based on the header part Ha for the information processing terminal a to transfer the transfer data Ta to the information processing terminal a on the outside.
If the transfer of the transfer data to the information processing terminal a is completed, then a process similar to that described above is repetitively performed and, finally, the descriptor Dn for the information processing terminal n is transmitted from the central processing section 101 to the transfer processing section 102 through the shared bus 103 (refer to reference character t6 in FIG. 20). Then, the transfer data Tn formed from the header part Hn for the information processing terminal n and the main data D is transmitted from the central processing section 101 to the transfer processing section 102 through the shared bus 103 based on the descriptor Dn (refer to reference characters t7 to t9 in FIG. 20), and the transfer data Tn is transferred from the transfer processing section 102 to the information processing terminal n on the outside.
Here, different operation of data transfer by the information processing terminal 100 described herein above with reference to FIG. 16 is described with reference to FIGS. 21 and 22. FIG. 21 is a view illustrating a different example of data produced by the central processing section 101 of the conventional information processing terminal 100 shown in FIG. 16. FIG. 22 is a time chart illustrating a flow of data on the shared bus 103 upon data transfer by the information processing terminal 100 shown in FIG. 21.
In the data transfer by the information processing terminal 100 illustrated in FIG. 21, where the same main data D is to be transferred to a plurality of different information processing terminals 110, the central processing section 101 produces and stores header parts Ha, Hb, . . . and Hn similar to those described above individually for the plural information processing terminals a, b, . . . and n to which the main data D is to be transferred, respectively, and produces and stores the only one main data D to be transferred. Then, in order to individually combine the header parts Ha, Hb, . . . and Hn with the main data D and transfer resulting data to the information processing terminals a, b, and n, the central processing section 101 produces a descriptor D—D for a common data part (main data) corresponding to the main data D and a plurality of header part descriptors D-Ha, D-Hb, . . . and D-Hn corresponding to the header parts Ha, Hb, . . . and Hn, respectively.
Thereafter, the central processing section 101 uses the descriptor chaining function described hereinabove with reference to FIG. 19 to transmit the header part descriptors D-Ha, D-Hb, . . . and D-Hn for the information processing terminals a, b, . . . and n and the common data part descriptor D—D in a paired relationship to each other to the transfer processing section 102 (refer to an arrow mark (3) in FIG. 21). Further, the header parts Ha, Hb, . . . and Hn and the main data D are combined with each other to produce the transfer data Ta, Tb, and Tn, and the produced transfer data are transmitted to the information processing terminals a, b, . . . and n, respectively (refer to an arrow mark (4) in FIG. 21).
In particular, if such paired descriptors as described above are detected, then the transfer processing section 102 reads out the header parts and the main data individually from the central processing section 101 based on the descriptors, and transfers the transfer data each formed from a header part and the main data to the information processing terminals 110 based on the header parts.
At this time, as seen in FIG. 22, the descriptor D-Ha for the header part Ha for the information processing terminal a and the common data part descriptor D—D are transmitted in a paired relationship with each other from the central processing section 101 to the transfer processing section 102 through the shared bus 103 (refer to reference characters t1 and t2 in FIG. 22). Then, in accordance with the descriptors D-Ha and D—D, the header part Ha for the information processing terminal a and the main data D are transmitted in a paired relationship with each other from the central processing section 101 to the transfer processing section 102 through the shared bus 103 (refer to reference characters t3 to t5 in FIG. 22).
The data transfer controlling section 106 in the transfer processing section 102 controls the shared bus controlling section 104 based on the descriptors D-Ha and D—D to read out the header part Ha and the main data D from the central processing section 101 as described above. Thereafter, the data transfer controlling section 106 controls the external port controlling section 105 based on the header part Ha to transfer the transfer data Ta formed from the header part Ha for the information processing terminal a and the main data D to the information processing terminal a on the outside.
Then, if the transfer of the transfer data to the information processing terminal a is completed, then a process similar to that described above is repetitively performed, and finally, the descriptor D-Hn for the header part Hn for the information processing terminal n and the common data part descriptor D—D are transmitted in a paired relationship with each other from the central processing section 101 to the transfer processing section 102 through the shared bus 103 (refer to reference characters t7 and t8 in FIG. 22). Then, based on the descriptors D-Hn and D—D, the header part Hn for the information processing terminal n and the main data D are transmitted in a paired relationship with each other from the central processing section 101 to the transfer processing section 102 through the shared bust 103 (refer to reference characters t9 to t11 in FIG. 22), and the transfer data is transferred from the transfer processing section 102 to the information processing terminal n on the outside.
Incidentally, where the conventional technique described above with reference to FIGS. 20 and 22 is used in order to transfer data (main data D) having contents same as each other by the DMA transfer method from the information processing terminal 100 to a plurality of information processing terminals 110, a number of header parts, main data and descriptors for them equal to the number of the information processing terminals 110 which are transfer destinations pass on the shared bus 103. Accordingly, if the number of the information processing terminals 110 which are transfer destinations increases, then the same main data D passes on the shared bus 103 by a corresponding increased number of times as seen in FIGS. 20 and 22, and as a result, the efficiency of use of the shared bus 103 is deteriorated and the transfer performance is deteriorated.
Further, where the data transfer method which utilizes the descriptor chaining function described with reference to FIGS. 21 and 22 is used, not only a header part descriptor but also the main data descriptor D—D must pass on the shared bus 103 for each of the information processing terminals 110 which are transfer destinations. Therefore, as seen in FIG. 22, the same descriptor D—D passes many times on the shared bus 103, and also this deteriorates the efficiency of use of the shared bus and deteriorates the transfer performance.
On the other hand, while such various data (header parts, main data and descriptors) produced by the central processing section 101 of the information processing terminal 100 as seen in FIGS. 17 and 21 are transmitted from the central processing section 101 to the transfer processing section 102 through the shared bus 103, during transfer of the transfer data by the DMA transfer method, that is, within a period before the transfer processing section 102 completes the transfer of the transfer data to the different information processing terminals 110 which are transfer destinations, the shared bus 103 is occupied by the transfer of the transfer data. Therefore, where the transfer speed of a communication line which connects the transfer processing section 102 and the external information processing terminals 110 (a, b, . . . and n) which are transfer destinations is sufficiently higher than that of the shared bus 103, the data transfer capacity between the transfer processing section 102 and the information processing terminals 110 which are transfer destinations cannot be sufficiently utilized due to the low transfer speed of the shared bus 103.
If, in the situation wherein the transfer speed of the shared bus 103 is low in this manner, the same main data and descriptors pass many times on the shared bus 103 as described with reference to FIGS. 20 and 22, then the efficiency of use of the shared bus 103 significantly drops, and this significantly degrades the data transfer capacity of the communication line between the information processing terminals. Accordingly, it is demanded to raise the efficiency of use of the shared bus 103 as high as possible.
[Patent document 1]
Japanese Patent Laid-Open No. 2001-344194
[Patent document 2]
Japanese Patent Laid-Open No. 8-202650
[Patent document 3]
Japanese Patent Laid-Open No. 10-177541
[Patent document 4]
Japanese Patent Laid-Open No. 6-314251